Datasheet

Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 385 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
3 ABCS 0 R/W Asynchronous Base Clock Select
Selects the 1-bit-interval base clock in asynchronous mode.
The ABCS setting is valid in asynchronous mode (C/A = 0
in SMR).
0: SCI_0 operates on base clock with frequency of 16
times transfer rate
1: SCI_0 operates on base clock with frequency of 8 times
transfer rate
2
1
0
ACS2
ACS1
ACS0
0
0
0
R/W
R/W
R/W
Asynchronous Clock Source Select 2 to 0
These bits select the clock source in asynchronous mode
depending on the combination with the bit 7 (ACS3) in
SEMRB_0 (serial extended mode register B_0). When an
average transfer rate is selected, the base clock is set
automatically regardless of the ABCS value. Note that
average transfer rates support only 10.667 MHz, 16 MHz,
and 24 MHz, and not support other operating frequencies.
Set ACS3 to ACS0 when inputting the external clock (the
CKE1 bit in the SCR register is 1) in asynchronous mode
(the C/A bit in the SMR register is 0). Figures 12.3 and 12.4
show the setting examples.
ACS 3210
0000: External clock input
0001: 115.152 kbps average transfer rate (for φ =
10.667 MHz only) is selected (SCI_0 operates
on base clock with frequency of 16 times
transfer rate)
0010: 460.606 kbps average transfer rate (for φ =
10.667 MHz only) is selected (SCI_0 operates
on base clock with frequency of eight times
transfer rate)
0011: 921.569 kbps average transfer rate (for φ = 16
MHz only) is selected (SCI_0 operates on base
clock with frequency of eight times transfer rate)
0100: TPU clock input
The signal generated by TIOCA0, TIOCC0,
TIOCA1, and TIOCA2, which are the compare
match outputs for TPU_0 to TPU_2 or PWM
outputs, is used as a base clock. Note that
IRQ0 and IRQ1 cannot be used since TIOCA1
and TIOCA2 are used as outputs.