Datasheet

Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 366 of 698
REJ09B0074-0700
RxD
TxD
SCK
Clock
External clock
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
SCMR:
BRR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Smart card register
Bit rate register
SCMR
SSR
SCR
SMR
control
transmission
and reception
Baud rate
generator
BRR
Module data bus
RDR
TSRRSR
Detecting parity
Parity check
Legend:
TDR
Internal data bus
Bus interface
Figure 12.2 Block Diagram of SCI_2