Datasheet

Rev.7.00 Dec. 24, 2008 Page xxxix of liv
REJ09B0074-0700
Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) ...... 140
Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)........................... 141
Figure 6.16 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) ..... 142
Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) ...... 143
Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)........................... 144
Figure 6.19 Example of Wait State Insertion Timing................................................................ 146
Figure 6.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)................. 148
Figure 6.21 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)................. 148
Figure 6.22 Example of Idle Cycle Operation (1) ..................................................................... 150
Figure 6.23 Example of Idle Cycle Operation (2) ..................................................................... 151
Figure 6.24 Relationship between Chip Select (CS) and Read (RD)......................................... 152
Figure 6.25 Bus-Released State Transition Timing................................................................... 154
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC ...................................................................................... 158
Figure 7.2 Operation in Sequential Mode................................................................................ 179
Figure 7.3 Example of Sequential Mode Setting Procedure.................................................... 180
Figure 7.4 Operation in Idle Mode .......................................................................................... 181
Figure 7.5 Example of Idle Mode Setting Procedure............................................................... 182
Figure 7.6 Operation in Repeat mode...................................................................................... 184
Figure 7.7 Example of Repeat Mode Setting Procedure.......................................................... 185
Figure 7.8 Operation in Normal Mode .................................................................................... 187
Figure 7.9 Example of Normal Mode Setting Procedure......................................................... 188
Figure 7.10 Operation in Block Transfer Mode (BLKDIR = 0)................................................ 190
Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 1)................................................ 191
Figure 7.12 Operation Flow in Block Transfer Mode ............................................................... 192
Figure 7.13 Example of Block Transfer Mode Setting Procedure............................................. 193
Figure 7.14 Example of DMA Transfer Bus Timing................................................................. 196
Figure 7.15 Example of Short Address Mode Transfer ............................................................. 197
Figure 7.16 Example of Full Address Mode (Cycle Steal) Transfer ......................................... 198
Figure 7.17 Example of Full Address Mode (Burst Mode) Transfer......................................... 199
Figure 7.18 Example of Full Address Mode (Block Transfer Mode) Transfer ......................... 200
Figure 7.19 Example of DREQ Level Activated Normal Mode Transfer ................................. 201
Figure 7.20 Example of Multi-Channel Transfer ...................................................................... 202
Figure 7.21 Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt .................................................................................................... 204
Figure 7.22 Example of Procedure for Forcibly Terminating DMAC Operation...................... 204
Figure 7.23 Example of Procedure for Clearing Full Address Mode ........................................ 205
Figure 7.24 Block Diagram of Transfer End/Transfer Break Interrupt ..................................... 206
Figure 7.25 DMAC Register Update Timing ............................................................................ 207
Figure 7.26 Contention between DMAC Register Update and CPU Read................................ 208