Datasheet

Section 10 Watchdog Timer (WDT)
Rev.7.00 Dec. 24, 2008 Page 347 of 698
REJ09B0074-0700
Writing 0 to WOVF bit
Write to RSTE, RSTS bits
Address: H'FF76
Address: H'FF76
H'A5 H'00
15 8 7 0
H'5A Write data
15 8 7 0
Figure 10.7 Format of Data Written to RSTCSR (Example of WDT0)
Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read by using the
same method as for the general registers. TCSR, TCNT, and RSTCSR are allocated in addresses
H'FF74, H'FF75, and H'FF77 respectively.
10.5.2 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 10.8 shows this operation.
A
ddress
φ
Internal write
signal
TCNT input
clock
TCNT
NM
T
1
T
2
TCNT write cycle
Counter write data
Figure 10.8 Contention between TCNT Write and Increment