Datasheet

Section 10 Watchdog Timer (WDT)
Rev.7.00 Dec. 24, 2008 Page 340 of 698
REJ09B0074-0700
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal reset signal*
Reset
control
RSTCSR TCNT TSCR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
Clock
select
Internal clock
sources
Bus
interface
Module bus
TCSR:
TCNT:
RSTCSR:
Notes: When a sub-block is operating, φ will be φ
SUB
.
* The type of internal reset signal depends on a register setting.
Timer control/status register
Timer counter
Reset control/status register
WDT
Legend:
Internal bus
Figure 10.1 Block Diagram of WDT
10.2 Register Descriptions
The WDT has the following three registers. For details, refer to section 21, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different
method to normal registers. For details, refer to section 10.5.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
10.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the
TME bit in TCSR is cleared to 0.
10.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and selecting the timer mode.