Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 336 of 698
REJ09B0074-0700
Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T
2
state of a buffer register write cycle, the buffer operation takes precedence and
the write to the buffer register is not performed. Figure 9.51 shows the timing in this case.
Input capture
signal
Write signal
A
ddress
φ
TCNT
Buffer register write cycle
T
1
T
2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 9.51 Contention between Buffer Register Write and Input Capture
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and
counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing
takes precedence. Figure 9.52 shows the operation timing when a TGR compare match is specified
as the clearing source, and H'FFFF is set in TGR.
Counter
clearing signal
TCNT input
clock
φ
TCNT
TGF flag
Prohibited
TCFV flag
H'FFFF H'0000
Figure 9.52 Contention between Overflow and Counter Clearing