Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 334 of 698
REJ09B0074-0700
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T
2
state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write. Figure 9.48 shows the timing in this case.
Compare
match signal
Write signal
A
ddress
φ
Buffer register
address
Buffer
register
TGR write cycle
T
1
T
2
N
TGR
N M
Buffer register write data
Figure 9.48 Contention between Buffer Register Write and Compare Match
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T
1
state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 9.49 shows the timing in this case.
Input capture
signal
Read signal
A
ddress
φ
TGR address
TGR
TGR read cycle
T
1
T
2
M
Internal
data bus
X M
Figure 9.49 Contention between TGR Read and Input Capture