Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 332 of 698
REJ09B0074-0700
Contention between TCNT Write and Clear Operations: If the counter clear signal is generated
in the T
2
state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not
performed. Figure 9.45 shows the timing in this case.
Counter clear
signal
Write signal
A
ddress
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N H'0000
Figure 9.45 Contention between TCNT Write and Clear Operations
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T
2
state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 9.46 shows the timing in this case.
TCNT input
clock
Write signal
A
ddress
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N M
TCNT write data
Figure 9.46 Contention between TCNT Write and Increment Operations