Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 283 of 698
REJ09B0074-0700
Bit Bit Name Initial value R/W Description
4 BFA 0 R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal way,
or TGRA and TGRC are to be used together for buffer
operation. When TGRC is used as a buffer register,
TGRC input capture/output compare is not generated. In
channels 1 and 2, which have no TGRC, bit 4 is reserved.
It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
3
2
1
0
MD3
MD2
MD1
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Modes 3 to 0
These bits are used to set the timer operating mode.
MD3 is a reserved bit. In a write, the write value should
always be 0. See table 9.8, for details.
Table 9.8 MD3 to MD0
Bit 3 Bit2 Bit 1 Bit 0
MD3*
1
MD2*
2
MD1 MD0
Description
0 Normal operation 0
1 Reserved
0 PWM mode 1
0
1
1 PWM mode 2
0 Phase counting mode 1 0
1 Phase counting mode 2
0 Phase counting mode 3
0
1
1
1 Phase counting mode 4
1 × × × —
Legend:
×: Don’t care
Notes: 1. MD3 is reserved bit. In a write, it should be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.