Datasheet

Section 8 I/O Ports
Rev.7.00 Dec. 24, 2008 Page 234 of 698
REJ09B0074-0700
8.6.2 Port A Data Register (PADR)
PADR stores output data for the port A pins.
Bit Bit Name Initial Value R/W Description
7 to
4
⎯ Undefined ⎯ Reserved
These bits are undefined and cannot be modified.
3
2
1
0
PA3DR
PA2DR
PA1DR
PA0DR*
0
0
0
0
R/W
R/W
R/W
R/W
Store output data for a pin that functions as a general
output port.
Note: * Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read. This bit
cannot be modified.
8.6.3 Port A Register (PORTA)
PORTA indicates the pin states of the port A.
Bit Bit Name Initial Value R/W Description
7 to
4
⎯ Undefined ⎯ Reserved
These bits are undefined.
3
2
1
0
PA3
PA2
PA1
PA0*
2
⎯*
1
⎯*
1
⎯*
1
⎯*
1
R
R
R
R
If the port A is read while PADDR bits are set to 1, the
PADR value is read. If the port A is read while PADDR
bits are cleared to 0, the pin states are read.
Notes: 1. Determined by the states of pins PA3 to PA0.
2. Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read.