Datasheet

Rev.7.00 Dec. 24, 2008 Page xxv of liv
REJ09B0074-0700
7.6.1 DMAC Register Access during Operation........................................................... 207
7.6.2 Module Stop......................................................................................................... 208
7.6.3 Medium-Speed Mode........................................................................................... 208
7.6.4 Activation Source Acceptance ............................................................................. 209
7.6.5 Internal Interrupt after End of Transfer................................................................ 209
7.6.6 Channel Re-Setting .............................................................................................. 209
Section 8 I/O Ports .............................................................................................................. 211
8.1 Port 1................................................................................................................................. 216
8.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 216
8.1.2 Port 1 Data Register (P1DR)................................................................................ 217
8.1.3 Port 1 Register (PORT1)...................................................................................... 217
8.1.4 Pin Functions ....................................................................................................... 218
8.2 Port 3................................................................................................................................. 223
8.2.1 Port 3 Data Direction Register (P3DDR)............................................................. 223
8.2.2 Port 3 Data Register (P3DR)................................................................................ 224
8.2.3 Port 3 Register (PORT3)...................................................................................... 224
8.2.4 Port 3 Open-Drain Control Register (P3ODR) .................................................... 225
8.2.5 Pin Functions ....................................................................................................... 225
8.3 Port 4................................................................................................................................. 227
8.3.1 Port 4 Register (PORT4)...................................................................................... 227
8.3.2 Pin Function......................................................................................................... 227
8.4 Port 7................................................................................................................................. 228
8.4.1 Port 7 Data Direction Register (P7DDR)............................................................. 228
8.4.2 Port 7 Data Register (P7DR)................................................................................ 229
8.4.3 Port 7 Register (PORT7)...................................................................................... 230
8.4.4 Pin Functions ....................................................................................................... 231
8.5 Port 9................................................................................................................................. 232
8.5.1 Port 9 Register (PORT9)...................................................................................... 232
8.5.2 Pin Function......................................................................................................... 232
8.6 Port A................................................................................................................................ 233
8.6.1 Port A Data Direction Register (PADDR) ........................................................... 233
8.6.2 Port A Data Register (PADR).............................................................................. 234
8.6.3 Port A Register (PORTA).................................................................................... 234
8.6.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................ 235
8.6.5 Port A Open-Drain Control Register (PAODR) .................................................. 235
8.6.6 Pin Functions ....................................................................................................... 236
8.6.7 Port A Input Pull-Up MOS States........................................................................ 238
8.7 Port B (H8S/2218 Group Only) ........................................................................................ 239
8.7.1 Port B Data Direction Register (PBDDR)............................................................ 239
8.7.2 Port B Data Register (PBDR) .............................................................................. 240