Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 209 of 698
REJ09B0074-0700
7.6.4 Activation Source Acceptance
At the start of activation source acceptance, a low level is detected in both DREQ signal falling
edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt
request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low
level that occurs before execution of the DMABCRL write to enable transfer.
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ
signal low level remaining from the end of the previous transfer, etc.
7.6.5 Internal Interrupt after End of Transfer
When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt
request will be sent to the CPU even if DTA is set to 1.
Also, if internal DMAC activation has already been initiated when operation is aborted, the
transfer is executed but flag clearing is not performed for the selected internal interrupt even if
DTA is set to 1.
An internal interrupt request following the end of transfer or an abort should be handled by the
CPU as necessary.
7.6.6 Channel Re-Setting
To reactivate a number of channels when multiple channels are enabled, use exclusive handling of
transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in
particular, that in cases where multiple interrupts are generated between reading and writing of
DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR
write data in the original interrupt handling routine will be incorrect, and the write may invalidate
the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR
operations are not performed by multiple interrupts, and that there is no separation between read
and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME
bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0
before the CPU can write a 1 to them.