Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 199 of 698
REJ09B0074-0700
Full Address Mode (Burst Mode): Figure 7.17 shows a transfer example in which TEND* output
is enabled and word-size full address mode transfer (burst mode) is performed from external 16-
bit, 2-state access space to external 16-bit, 2-state access space.
φ
DMA read
RD
HWR
TEND*
LWR
DMA write
DMA read DMA write DMA read DMA write
DMA
dead
A
ddress bus
Bus release Bus release
Last transfer cycle
Burst transfer
Note: * This LSI does not support TEND output.
Figure 7.17 Example of Full Address Mode (Burst Mode) Transfer
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the
transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle
is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state,
the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer
has already been activated inside the DMAC, the bus is released on completion of a one-byte or
one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer
cycle of the burst transfer has already been activated inside the DMAC, execution continues to the
end of the transfer even if the DTME bit is cleared.
Note: * This LSI does not support TEND output.