Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 198 of 698
REJ09B0074-0700
Full Address Mode (Cycle Steal Mode): Figure 7.16 shows a transfer example in which TEND*
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
φ
DMA read
RD
HWR
TEND*
LWR
DMA write DMA read DMA write DMA read DMA write
DMA
dead
A
ddress bus
Bus release Bus release Bus release Bus releas
e
Last transfer cycle
Note: * This LSI does not support TEND output.
Figure 7.16 Example of Full Address Mode (Cycle Steal) Transfer
A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the
bus is released one bus cycle is inserted by the CPU.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Note: * This LSI does not support TEND output.