Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 196 of 698
REJ09B0074-0700
7.4.8 Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.14. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings.
DMAC cycle (1-word transfer) CPU cycleCPU cycle
T
1
T
2
T
1
T
2
T
3
T
1
T
2
T
3
Source
address
Destination address
φ
Address bus
RD
HWR
LWR
Figure 7.14 Example of DMA Transfer Bus Timing
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.