Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 187 of 698
REJ09B0074-0700
Figure 7.8 illustrates operation in normal mode.
A
ddress T
A
A
ddress B
A
Transfer
Address T
B
Notes:
Address T
A
= L
A
Address T
B
= L
B
Address B
A
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N–1))
Address B
B
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (N–1))
L
A
= Value set in MARA
L
B
= Value set in MARB
N = Value set in ETCRA
Address B
B
Figure 7.8 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests. With auto-request,
the DMAC is only activated by register setting, and the specified number of transfers are
performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In
cycle steal mode, the bus is released to another bus master each time a transfer is performed. In
burst mode, the bus is held continuously until transfer ends. For setting details, see section 7.3.4,
DMA Controller Register (DMACR).