Datasheet

Rev.7.00 Dec. 24, 2008 Page xxii of liv
REJ09B0074-0700
2.8 Processing States ............................................................................................................... 64
2.9 Usage Notes....................................................................................................................... 66
2.9.1 Note on TAS Instruction Usage ........................................................................... 66
2.9.2 STM/LTM Instruction Usage............................................................................... 66
2.9.3 Note on Bit Manipulation Instructions ................................................................. 66
2.9.4 Accessing Registers Containing Write-Only Bits ................................................ 68
Section 3 MCU Operating Modes................................................................................... 71
3.1 Operating Mode Selection................................................................................................. 71
3.2 Register Descriptions......................................................................................................... 72
3.2.1 Mode Control Register (MDCR).......................................................................... 72
3.2.2 System Control Register (SYSCR) ...................................................................... 72
3.3 Operating Mode Descriptions............................................................................................ 74
3.3.1 Mode 4 (Supported Only by the H8S/2218 Group).............................................. 74
3.3.2 Mode 5 (Supported Only by the H8S/2218 Group).............................................. 74
3.3.3 Mode 6 (Supported Only by the H8S/2218 Group).............................................. 75
3.3.4 Mode 7 ................................................................................................................. 75
3.3.5 Pin Functions........................................................................................................ 76
3.4 Memory Map in Each Operating Mode............................................................................. 77
Section 4 Exception Handling.......................................................................................... 81
4.1 Exception Handling Types and Priority ............................................................................ 81
4.2 Exception Sources and Exception Vector Table................................................................ 81
4.3 Reset .................................................................................................................................. 83
4.3.1 Reset Types .......................................................................................................... 83
4.3.2 Reset Exception Handling .................................................................................... 84
4.3.3 Interrupts after Reset ............................................................................................ 86
4.3.4 State of On-Chip Peripheral Modules after Reset Release ................................... 86
4.4 Traces ................................................................................................................................ 87
4.5 Interrupts ........................................................................................................................... 87
4.6 Trap Instruction ................................................................................................................. 88
4.7 Stack Status after Exception Handling .............................................................................. 89
4.8 Notes on Use of the Stack ................................................................................................. 90
Section 5 Interrupt Controller........................................................................................... 91
5.1 Features ............................................................................................................................. 91
5.2 Input/Output Pins .............................................................................................................. 93
5.3 Register Descriptions......................................................................................................... 93
5.3.1 Interrupt Priority Registers A to G, J, K, M
(IPRA to IPRG, IPRJ, IPRK, IPRM) ................................................................... 94
5.3.2 IRQ Enable Register (IER)................................................................................... 95