Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 181 of 698
REJ09B0074-0700
7.4.3 Idle Mode
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The
transfer direction can be specified by the DTDIR bit in DMACR. Table 7.4 summarizes register
functions in idle mode.
Table 7.4 Register Functions in Idle Mode
Function
Register DTDIR = 0 DTDIR = 1 Initial Setting Operation
23 0
MAR
Source
address
register
Destination
address
register
Start address of
transfer destination
or transfer source
Fixed
23 15 0
IOARH'FF
Destination
address
register
Source
address
register
Start address of
transfer source or
transfer destination
Fixed
015
ETCR
Transfer counter Number of transfers Decremented every
transfer, transfer
ends when count
reaches H'0000
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.4
illustrates operation in idle mode.
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
MAR
Figure 7.4 Operation in Idle Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If
the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU. The maximum number
of transfers, when H'0000 is set in ETCR, is 65,536.