Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 179 of 698
REJ09B0074-0700
A
ddress T
A
ddress B
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Notes:
Address
Address
Where:
T = L
B = L + (–1)
DTID
· (2
DTSZ
· (N–1))
L = Value set in MAR
N = Value set in ETCR
Figure 7.2 Operation in Sequential Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If
the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU. The maximum number
of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist
of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and
TPU channel 0 to 2 compare match/input capture A interrupts. Figure 7.3 shows an example of the
setting procedure for sequential mode.