Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 170 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
11
10
9
8
DTA1B
DTA1A
DTA0B
DTA0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Acknowledge
These bits enable or disable clearing, when DMA transfer is
performed, of the internal interrupt source selected by the
data transfer factor setting.
When DTE = 1 and DTA = 1, the internal interrupt source
selected by the data transfer factor setting is cleared
automatically by DMA transfer. When DTE = 1 and DTA = 1,
the internal interrupt source selected by the data transfer
factor setting does not issue an interrupt request to the CPU.
When DTE = 1 and DTA = 0, the internal interrupt source
selected by the data transfer factor setting is not cleared
when a transfer is performed, and can issue an interrupt
request to the CPU in parallel. In this case, the interrupt
source should be cleared by the CPU.
When DTE = 0, the internal interrupt source selected by the
data transfer factor setting issues an interrupt request to the
CPU regardless of the DTA bit setting.
0: Clearing of selected internal interrupt source at time of
DMA transfer is disabled
1: Clearing of selected internal interrupt source at time of
DMA transfer is enabled