Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 168 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Factor
These bits select the data transfer factor (activation source).
In normal mode:
0000: ⎯
0001: ⎯
0010: ⎯
0011: Activated by DREQ signal's low level input from USB
(USB request)
010×: ⎯
0110: Auto-request (cycle steal)
0111: Auto-request (burst)
1×××: ⎯
In block transfer mode:
0000: ⎯
0001: Activated by A/D conversion end interrupt
0010: ⎯
0011: ⎯
0100: Activated by SCI channel 0 transmission complete
interrupt
0101: Activated by SCI channel 0 reception complete
interrupt
0110: ⎯
0111: ⎯
1000: Activated by TPU channel 0 compare match/input
capture A interrupt
1001: Activated by TPU channel 1 compare match/input
capture A interrupt
1010: Activated by TPU channel 2 compare match/input
capture A interrupt
1011: ⎯
11××: ⎯
The same factor can be selected for more than one channel.
In this case, activation starts with the highest-priority channel
according to the relative channel priorities. For relative
channel priorities, see section 7.4.10, DMAC Multi-Channel
Operation.
Legend:
×: Don't care