Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 167 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
10
to
8
⎯ All 0 R/W Reserved
Although these bits are readable/writable, only 0 should be
written to.
• Full Address Mode (DMACRB)
Bit Bit Name Initial Value R/W Description
7 ⎯ 0 R/W Reserved
Although this bit is readable/writable, only 0 should be written
to.
6
5
DAID
DAIDE
0
0
R/W
R/W
Destination Address Increment/Decrement
Destination Address Increment/Decrement Enable
These bits specify whether destination address register
MARB is to be incremented, decremented, or left unchanged,
when data transfer is performed.
00: MARB is fixed
01: MARB is incremented after a data transfer
• When DTSZ = 0, MARB is incremented by 1 after a
transfer
• When DTSZ = 1, MARB is incremented by 2 after a
transfer
10: MARB is fixed
11: MARB is decremented after a data transfer
• When DTSZ = 0, MARB is decremented by 1 after a
transfer
• When DTSZ = 1, MARB is decremented by 2 after a
transfer
4 ⎯ 0 R/W Reserved
Although this bit is readable/writable, only 0 should be written
to.