Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 153 of 698
REJ09B0074-0700
6.9 Bus Release
The H8S/2218 Group can release the external bus in response to a bus request from an external
device. In the external bus released state, the internal bus master continues to operate as long as
there is no external access.
In external extended mode, the bus can be released to an external device by setting the BRLE bit in
BCRL to 1. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ
pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus,
and bus control signals are placed in the high-impedance state, establishing the external bus-
released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers activation
of the bus cycle, and waits for the bus request from the external bus master to be dropped.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
In the event of simultaneous external bus release request and external access request generation,
the order of priority is as follows:
(High) External bus release > Internal bus master external access (Low)
Table 6.5 shows pin states in the external bus released state.
In the H8S/2212 Group, the BRLE bit in BCRL should not be set to 1.
Table 6.5 Pin States in Bus Released State
Pins Pin State
A23 to A0 High impedance
D15 to D0 High impedance
CSn High impedance
AS High impedance
RD High impedance
HWR High impedance
LWR High impedance