Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 144 of 698
REJ09B0074-0700
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
D7 to D0
Valid
Valid
Read
HWR
LWR
D15 to D8
D7 to D0
Valid
Valid
Write
Note: n = 0 to 5
T
3
Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
