Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 133 of 698
REJ09B0074-0700
T
1
T
2
Bus cycle
Unchanged
A
ddress bus*
AS*
RD*
HWR, LWR*
Data bus*
Note: * Supported only by the H8S/2218 Group.
φ
High
High
High
High-impedance state
Figure 6.7 Pin States during On-Chip Peripheral Module Access
6.5.3 External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 6.6.3, Basic Timing.