Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 130 of 698
REJ09B0074-0700
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space.
Only the basic bus interface can be used for the area 7.
6.4.4 Chip Select Signals
In the H8S/2218 Group chip select signals (CS0 to CS5) can be output to areas 0 to 5, the signal
being driven low when the corresponding external space area is accessed. Figure 6.3 shows an
example of CSn (n = 0 to 5) output timing. Enabling or disabling of the CSn signal is performed
by setting the data direction register (DDR) for the port corresponding to the particular CSn pin.
In ROM-disabled extended mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS5 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS1 to CS5.
In ROM-enabled extended mode, pins CS0 to CS5 are all placed in the input state after a power-on
reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS5. For
details, see section 8, I/O Ports.
Bus cycle
T
1
T
2
T
3
Area n external address
A
ddress bus
φ
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 5)