Datasheet

Rev.7.00 Dec. 24, 2008 Page xv of liv
REJ09B0074-0700
Item Page Revision (See Manual for Details)
13.3.2 IDCODE
Register (IDCODE)
454 Description amended
...The HD64F2218, HD64F2218U, HD64F2218CU and
HD64F2217CU output fixed codes H'002A200F from the TDO.
...
Table 13.3 IDCODE
Register Configuration
Table amended
Bits
HD64F2218,
HD64F2218U,
HD64F2218CU and
HD64F2217CU codes
Contents
14.3.5 USB FIFO
Clear Register 0
(UFCLR0)
475 to
476
Bit Table amended
Bit Bit Name Initial Value R/W Description
7, 6 — All 0 R Reserved
These bits are always rea
modified.
5 EP2CLR 0 W EP2 Clear*
0: Performs no operation.
1: Clears EP2 OUT FIFO.
Note added
Note:* When DMA writes are enabled (EP2T1 set to 1 and
EP2T0 set to 0 or 1 in UDMAR), it is not possible to
clear the data in the FIFO by writing 1 to EP2CLR. To
clear the data in the FIFO, disable DMA transfers (clear
EP2T1 and EP2T0 in UDMAR to 0) and then write 1 to
EP2CLR.
14.8.16 Clearing the
FIFO when DMA
Transfer Is Enabled
533 Description added
When DMA transfer is enabled (EP2T1 = 1 and EP2T0 = 0 or 1
in UDMAR) at endpoint 2, it is not possible to clear OUTFIFO in
EP2. It is necessary to disable DMA transfer (EP2T1 = 0 and
EP2T0 = 0 in UDMAR) before clearing the FIFO.
Section 16 RAM 551 Description amended
The HD64F2218, HD64F2218U, and HD64F2218CU have 12
kbytes of on-chip high-speed static RAM. The HD6432217,
HD64F2211, HD64F2211U, and HD64F2211CU have 8 kbytes
of on-chip high-speed static RAM. The HD6432210 and
HD6432210S have 4 kbytes of on-chip high-speed static RAM.
The RAM is connected to the CPU by a 16-bit data bus,
enabling one-state access by the CPU to both byte data and
word data.