Datasheet

Section 5 Interrupt Controller
Rev.7.00 Dec. 24, 2008 Page 100 of 698
REJ09B0074-0700
The set timing for IRQnF is shown in figure 5.3.
IRQn
input pin
IRQnF
φ
Note: n = 7 to 0
Figure 5.3 Timing of Setting IRQnF
The detection of IRQn interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0; and use the pin as an I/O pin for another function. IRQnF interrupt
request flag is set when the setting condition is satisfied, regardless of IER settings. Accordingly,
refer to only necessary flags.
5.4.2 Internal Interrupts
The sources for internal interrupts from on—chip peripheral modules have the following features:
• For each on—chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC is activated by an interrupt request, it is not affected by the interrupt control
mode or CPU interrupt mask bit.