Datasheet

Section 5 Interrupt Controller
Rev.7.00 Dec. 24, 2008 Page 98 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
1
0
IRQ0SCB
IRQ0SCA
0
0
R/W
R/W
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input low level
01: Interrupt request generated at falling edge of IRQ0
input
10: Interrupt request generated at rising edge of IRQ0
input
11: Interrupt request generated at both falling and
rising edges of IRQ0 input
Legend:
×: Don’t care
Notes: 1. IRQ6 is an interrupt only for the on-chip USB.
2. IRQ5 is an interrupt only for the on-chip RTC.
5.3.4 IRQ Status Register (ISR)
ISR indicates the status of IRQ7 to IRQ0 interrupt requests.
Bit Bit Name Initial Value R/W Description
7 IRQ7F 0 R/(W)*
6 IRQ6F 0 R/(W)*
5 IRQ5F 0 R/(W)*
4 IRQ4F 0 R/(W)*
3 IRQ3F 0 R/(W)*
2 IRQ2F 0 R/(W)*
1 IRQ1F 0 R/(W)*
0 IRQ0F 0 R/(W)*
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
• Cleared by reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
• When interrupt exception handling is executed
when low-level detection is set and , IRQn input is
high
• When IRQn interrupt exception handling is executed
when falling, rising, or both-edge detection is set
Note: * Only 0 can be written, to clear flags.