Datasheet

Section 5 Interrupt Controller
Rev.7.00 Dec. 24, 2008 Page 96 of 698
REJ09B0074-0700
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0.
Bit Bit Name Initial Value R/W Description
15
14
IRQ7SCB
IRQ7SCA
0
0
R/W
R/W
IRQ7 Sense Control B
IRQ7 Sense Control A
00: Interrupt request generated at IRQ7 input low level
01: Interrupt request generated at falling edge of IRQ7
input
10: Interrupt request generated rising edge of IRQ7
input
11: Interrupt request generated at both falling and
rising edges of IRQ7 input
13
12
IRQ6SCB
IRQ6SCA
0
0
R/W
R/W
IRQ6*
1
Sense Control B
IRQ6*
1
Sense Control A
00: Setting prohibited when using on-chip USB
suspend or resume interrupt
01: Interrupt request generated at falling edge of IRQ6
input
1x: Setting prohibited
11
10
IRQ5SCB
IRQ5SCA
0
0
R/W
R/W
IRQ5*
2
Sense Control B
IRQ5*
2
Sense Control A
00: Setting prohibited when using RTC interrupt
01: Interrupt request generated at falling edge of IRQ5
input
1x: Setting prohibited
9
8
IRQ4SCB
IRQ4SCA
0
0
R/W
R/W
IRQ4 Sense Control B
IRQ4 Sense Control A
00: Interrupt request generated at IRQ4 input low level
01: Interrupt request generated at falling edge of IRQ4
input
10: Interrupt request generated at rising edge of IRQ4
input
11: Interrupt request generated at both falling and
rising edges of IRQ4 input