Datasheet

Section 5 Interrupt Controller
Rev.7.00 Dec. 24, 2008 Page 94 of 698
REJ09B0074-0700
5.3.1 Interrupt Priority Registers A to G, J, K, M (IPRA to IPRG, IPRJ, IPRK, IPRM)
The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI.
The correspondence between interrupt sources and IPR settings is shown in section 5.5, Interrupt
Exception Handling Vector Table. Setting a value in the range from H'0 to H'7 in the 3-bit groups
of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.
Bit Bit Name Initial Value R/W Description
7 – 0 – Reserved
This bit is always read as 0 and cannot be modified.
6
5
4
IPR6
IPR5
IPR4
1
1
1
R/W
R/W
R/W
These bits set the priority of the corresponding
interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
3 – 0 – Reserved
This bit is always read as 0 and cannot be modified.
2
1
0
IPR2
IPR1
IPR0
1
1
1
R/W
R/W
R/W
These bits set the priority of the corresponding
interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)