Datasheet

Section 2 CPU
Rev.7.00 Dec. 24, 2008 Page 51 of 698
REJ09B0074-0700
Table 2.6 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents. 1-bit or 2 bit
shift is possible.
SHLL
SHLR
B/W/L Rd (shift) → Rd
Performs an logical shift on general register contents. 1-bit or 2 bit shift is
possible.
ROTL
ROTR
B/W/L Rd (rotate) → Rd
Rotates general register contents. 1-bit or 2 bit rotation is possible.
ROTXL
ROTXR
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag. 1-bit or 2 bit
rotation is possible.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword