Datasheet

Rev. 3.00, 03/04, page 56 of 830
Bit Bit Name Initial Value R/W Description
1 KINWUE 0 R/W Keyboard Control Register Access Enable
Enables or disables CPU access for input control
registers (KMIMRA, KMIMR6, WUEMR3) of KINn and
WUEn pins, input pull-up MOS control register
(KMPCR6) of the KINn pin, and registers
(TCR_X/TCR_Y, TCSR_X/TCSR_Y,
TICRR/TCORA_Y, TICRF/TCORB_Y,
TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X,
TCORB_X) of 8-bit timers (TMR_X, TMR_Y),
0: Enables CPU access for registers of TMR_X and
TMR_Y in an area from H'FFFFF0 to H'FFFFF7 and
from H'FFFFFC to H'FFFFFF.
1: Enables CPU access for input control registers of
the KINn and WUEn pins and the input pull-up MOS
control register of the KINn pin in an area from
H'FFFFF0 to H'FFFFF7 and from H'FFFFFC to
H'FFFFFF.
0 RAME 1 R/W RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
3.2.3 Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit Bit Name Initial Value R/W Description
7
6
5
IICX2
IICX1
IICX0
0
0
0
R/W
R/W
R/W
IIC Transfer Rate Select 2, 1 and 0
These bits control the IIC operation. These bits
select a transfer rate in master mode together with
bits CKS2 to CKS0 in the I
2
C bus mode register
(ICMR). For details on the transfer rate, see table
15.3. The IICXn bit controls IIC_n. (n = 0 to 2)