Datasheet

Rev. 3.00, 03/04, page 818 of 830
Port Name
Pin Name
MCU
Operating
Mode Reset
Hardware
Standby
Mode
Software
Standby
Mode
Watch
Mode
Sleep
Mode
Subsleep
Mode
Subactive
Mode
Program
Execution
State
Port 95 to 93
AS, IOS,
HWR, RD
(EXPE = 1) T T H H H H AS/IOS,
HWR/RD
AS/IOS,
HWR/RD
(EXPE = 0) kept kept kept kept I/O port I/O port
Port 92 and
91
CPCS1
(EXPE = 1) T T kept kept kept kept CPCS1/
I/O port
CPCS1/
I/O port
(EXPE = 0) I/O port I/O port
Port 90
LWR
(EXPE = 1) T T H/kept H/kept H/kept H/kept LWR/
I/O port
LWR/
I/O port
(EXPE = 0) kept kept kept kept I/O port I/O port
Port A
A23 to A16
(EXPE = 1) T T kept* kept* kept* kept* Address
output/
I/O port
Address
output/
I/O port
(EXPE = 0) I/O port I/O port
Port B
(EXPE = 1) T T kept kept kept kept I/O port I/O port
(EXPE = 0)
Port C
(EXPE = 1) T T kept kept kept kept I/O port I/O port
(EXPE = 0)
Port D
(EXPE = 1) T T kept kept kept kept I/O port I/O port
(EXPE = 0)
Port E
(EXPE = 1) T T kept kept kept kept I/O port I/O port
(EXPE = 0)
Port F
(EXPE = 1) T T kept kept kept kept I/O port I/O port
(EXPE = 0)
Legend
H: High level
L: Low level
T: High impedance
kept: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up
MOS remains on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR.
DDR: Data direction register
Note: * In the case of address output, the last address accessed is retained.