Datasheet

Rev. 3.00, 03/04, page 809 of 830
LCLK
LAD3 to LAD0,
SERIRQ, CLKRUN
(Transmit signal)
LAD3 to LAD0,
SERIRQ, CLKRUN,
LFRAME
(Receive signal)
t
TXD
t
RXH
t
RXS
t
OFF
LAD3 to LAD0,
SERIRQ, CLKRUN
(Transmit signal)
t
Lcyc
t
LCKH
LCLK
t
LCKL
Figure 25.31 LPC Interface (LPC) Timing
Table 25.13 JTAG Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item Symbol Min. Max. Unit Test Conditions
ETCK clock cycle time t
TCKcyc
40* 200* ns Figure 25.32
ETCK clock high pulse width t
TCKH
15 
ETCK clock low pulse width t
TCKL
15 
ETCK clock rise time t
TCKr
 5
ETCK clock fall time t
TCKf
 5
ETRST pulse width t
TRSTW
20  t
cyc
Figure 25.33
Reset hold transition pulse width t
RSTHW
3 
ETMS setup time t
TMSS
20  ns Figure 25.34
ETMS hold time t
TMSH
20 
ETDI setup time t
TDIS
20 
ETDI hold time t
TDIH
20 
ETDO data delay time t
TDOD
 20
Note: * When t
cyc
≤ t
TCKcyc