Datasheet

Rev. 3.00, 03/04, page 808 of 830
t
BUF
t
STAH
t
STAS
t
SP
t
STOS
t
SCLH
t
SCLL
t
Sf
t
Sr
t
SCL
t
SDAH
t
SDAS
P* S* Sr*
P*
V
IH
V
IL
SDA0
to
SDA5
SCL0
to
SCL5
Note: * S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Retransmission start condition
Figure 25.30 I
2
C Bus Interface Input/Output Timing
Table 25.12 LPC Module Timing
Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item Symbol Min. Typ. Max. Unit Test Conditions
Input clock cycle t
Lcyc
30   ns Figure 25.31
Input clock pulse width (H) t
LCKH
11  
Input clock pulse width (L) t
LCKL
11  
Transmit signal delay time t
TXD
2  11
Transmit signal floating
delay time
t
OFF
  28
Receive signal setup time t
RXS
7  
Receive signal hold time t
RXH
0  