Datasheet

Rev. 3.00, 03/04, page 807 of 830
Table 25.11 I
2
C Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item Symbol Min. Typ. Max. Unit Test Conditions
SCL input cycle time t
SCL
12   t
cyc
SCL input high pulse width t
SCLH
3  
SCL input low pulse width t
SCLL
5  
SCL, SDA input rise time t
Sr
  7.5*
SCL, SDA input fall time t
Sf
  300 ns
SCL, SDA output fall time t
Of
20 + 0.1 C
b
 250
SCL, SDA input spike
pulse elimination time
t
SP
  1 t
cyc
SDA input bus free time t
BUF
5  
Start condition input hold
time
t
STAH
3  
Retransmission start
condition input setup time
t
STAS
3  
Stop condition input setup
time
t
STOS
3  
Data input setup time t
SDAS
0.5  
Data input hold time t
SDAH
0   ns
SCL, SDA capacitive load C
b
  400 pF
Figure 25.30
Note: * 17.5 t
cyc
or 37.5 t
cyc
can be set according to the clock selected for use by the IIC module.