Datasheet

Rev. 3.00, 03/04, page 803 of 830
Table 25.10 Timing of On-Chip Peripheral Modules
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz*, φ = 5 MHz to 33 MHz
Item Symbol Min. Max. Unit Test Conditions
I/O ports Output data delay time t
PWD
 30 ns
Input data setup time t
PRS
20 
Input data hold time t
PRH
20 
Figure 25.19
FRT Timer output delay time t
FTOD
 30 ns
Timer input setup time t
FTIS
20 
Figure 25.20
Timer clock input setup time t
FTCS
20 
Single edge t
FTCWH
1.5  t
cyc
Timer clock
pulse width
Both edges t
FTCWL
2.5 
Figure 25.21
TMR Timer output delay time t
TMOD
 30 ns Figure 25.22
Timer reset input setup time t
TMRS
20  Figure 25.24
Timer clock input setup time t
TMCS
20 
Single edge t
TMCWH
1.5  t
cyc
Timer clock
pulse width
Both edges t
TMCWL
2.5 
Figure 25.23
PWM,
PWMX
Timer output delay time t
PWOD
 30 ns Figure 25.25
SCI Input clock cycle Asynchronous t
Scyc
4  t
cyc
Synchronous 6 
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
 1.5 t
cyc
Input clock fall time t
SCKf
 1.5
Figure 25.26
Transmit data delay time
(synchronous)
t
TXD
 30 ns
Receive data setup time
(synchronous)
t
RXS
20 
Receive data hold time
(synchronous)
t
RXH
20 
Figure 25.27
A/D
converter
Trigger input setup time t
TRGS
20  ns Figure 25.28
WDT RESO output delay time t
RESD
 200 ns
RESO output pulse width t
RESOW
132  t
cyc
Figure 25.29
Note: * Only the peripheral modules that can be used in subclock operation.