Datasheet

Rev. 3.00, 03/04, page 801 of 830
φ
AH
RD
(Read)
T
1
T
2
AD15 to AD0
(Read)
D15 to D0
D15 to D0
A15 to A0
A15 to A0
HWR, LWR
(Write)
AD15 to AD0
(Write)
T
3
T
4
t
CSD
t
AHD
t
RSD1
t
ACC2
t
ACC6
t
AS2
t
AD
t
AD
t
AH2
t
WRD2
t
WDD
t
WDH
t
RSD2
t
WRD2
t
WSW1
t
RDS
t
RDH
IOS, CS256,
CPCS1
Figure 25.17 Multiplex Bus Timing/Data 2-State Access
T
1
T
2
T
3
T
4
T
5
t
CSD
t
AHD
t
RSD1
t
ACC4
t
ACC7
t
AS2
t
AD
t
AD
t
AH2
t
WRD1
t
WDD
t
WDH
t
WDS
t
RSD2
t
WRD2
t
WSW2
t
RDS
t
RDH
φ
AH
RD
(Read)
AD15 to AD0
(Read)
D15 to D0
D15 to D0
A15 to A0
A15 to A0
HWR, LWR
(Write)
AD15 to AD0
(Write)
IOS, CS256,
CPCS1
Figure 25.18 Multiplex Bus Timing/Data 3-State Access