Datasheet

Rev. 3.00, 03/04, page 800 of 830
25.3.4 Multiplex Bus Timing
Table 25.9 shows the Multiplex bus interface timing. In subclock (φSUB = 32.768 kHz) operation,
external expansion mode operation cannot be guaranteed.
Table 25.9 Multiplex Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item Symbol Min.. Max. Unit Test Conditions
Address delay time t
AD
— 15 ns Figures 25.17,
Address setup time 2 t
AS2
0.5 × t
cyc
− 15 — 25.18
Address hold time 2 t
AH2
1.0 × t
cyc
− 10 —
CS delay time (IOS,
CS256, CPCS1)
t
CSD
— 15
AH delay time t
AHD
— 15
RD delay time 1 t
RSD1
— 15
RD delay time 2 t
RSD2
— 15
Read data setup time t
RDS
15 —
Read data hold time t
RDH
0 —
Read data access time 2 t
ACC2
— 1.5 × t
cyc
− 25
Read data access time 4 t
ACC4
— 2.5 × t
cyc
− 25
Read data access time 6 t
ACC6
— 3.5 × t
cyc
− 25
Read data access time 7 t
ACC7
— 4.5 × t
cyc
− 25
WR delay time 1 t
WRD1
— 15
WR delay time 2 t
WRD2
— 15
WR pulse width time 1 t
WSW1
1.0 × t
cyc
− 20 —
WR pulse width time 2 t
WSW2
1.5 × t
cyc
− 20 —
Write data delay time t
WDD
— 25
Write data setup time t
WDS
0 —
Write data hold time t
WDH
0.5 × t
cyc
− 5 —