Datasheet

Rev. 3.00, 03/04, page 791 of 830
t DEXT *
RES
(Internal and external)
EXTAL
STBY
VCC
2.7 V
V
IH
φ
Note: The external clock output stabilization delay time (t
DEXT ) includes a RES pulse width (t RESW ).
Figure 25.8 Timing of External Clock Output Stabilization Delay Time
t
EXCLH
t
EXCLL
t
EXCLr
t
EXCLf
V
CC
× 0.5
EXCL
Figure 25.9 Subclock Input Timing