Datasheet

Rev. 3.00, 03/04, page 789 of 830
Table 25.5 External Clock Input Conditions
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item Symbol Min. Max. Unit
Test
Conditions
External clock input low level
pulse width
t
EXL
10  ns
External clock input high level
pulse width
t
EXH
10  ns
External clock input rising time t
EXr
 5 ns
External clock input falling time t
EXf
 5 ns
Figure 25.7
Clock low level pulse width t
CL
0.4 0.6 t
cyc
Clock high level pulse width t
CH
0.4 0.6 t
cyc
Figure 25.4
External clock output
stabilization delay time
t
DEXT
* 500  µs Figure 25.8
Note: * t
DEXT
includes a RES pulse width (t
RESW
).
Table 25.6 Subclock Input Conditions
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz, 5 MHz to 33 MHz
Item Symbol Min. Typ. Max. Unit
Measureme
nt Condition
Subclock input low level pulse
width
t
EXCLL
 15.26  µs
Subclock input high level pulse
width
t
EXCLH
 15.26  µs
Subclock input rising time t
EXCLr
  10 ns
Subclock input falling time t
EXCLf
  10 ns
Figure 25.9
Clock low level pulse width t
CL
0.4  0.6 t
cyc
Clock high level pulse width t
CH
0.4  0.6 t
cyc
Figure 25.4
t
Cr
t
CL
t
Cf
t
cyc
t
CH
φ
Figure 25.4 System Clock Timing