Datasheet
Rev. 3.00, 03/04, page 773 of 830
24.3 Register States in Each Operating Mode
Register
Abbrevia-
tion
Reset
High-Speed/
Medium-
Speed
Watch Sleep Sub-Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby
Module
HICR4 Initialized Initialized
BTSR0 Initialized Initialized
BTSR1 Initialized Initialized
BTCSR0 Initialized Initialized
BTCSR1 Initialized Initialized
BTCR Initialized Initialized
BTIMSR Initialized Initialized
SMICFLG Initialized Initialized
SMICCSR
SMICDTR
SMICIR0 Initialized Initialized
SMICIR1 Initialized Initialized
TWR0MW
TWR0SW
TWR1
TWR2
TWR3
TWR4
TWR5
TWR6
TWR7
TWR8
TWR9
TWR10
TWR11
TWR12
TWR13
TWR14
TWR15
IDR3
ODR3
LPC