Datasheet

Rev. 3.00, 03/04, page 736 of 830
Program halt state
Program execution state
SCK2 to
SCK0 are
0
SCK2 to
SCK0 are
not 0
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
Clock switching
exception processing
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
After the oscillation
stabilization time
(STS2 to STS0), clock
switching exception
processing
SLEEP instruction
SLEEP
instruction
External
interrupt *
3
Any interrupt
SLEEP
instruction
SLEEP
instruction
SLEEP instruction
Interrupt *
1
LSON bit = 0
Interrupt *
2
Interrupt *
1
LSON bit = 1
STBY pin = High
RES pin = Low
STBY pin = Low
SSBY = 0, LSON = 0
SSBY = 1,
PSS = 0, LSON = 0
SSBY = 0,
PSS = 1, LSON = 1
SSBY = 1,
PSS = 1, DTON = 0
RES pin = High
: Transition after exception processing : Power-down mode
Reset state
High-speed mode
(main clock)
Medium-speed
mode
(main clock)
Subactive mode
(subclock)
Subsleep mode
(subclock)
Hardware
standby mode
Software
standby mode
Sleep mode
(main clock)
Watch mode
(subclock)
Notes:
1.
2.
3.
NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and WDT_1 interrupts
NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, WDT_0, WDT_1, TMR_0,
and TMR_1 interrupts
NMI, IRQ0 to IRQ15, KIN0 to KIN15, and WUE8 to WUE15 interrupts
• When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the
interrupt request.
• Always select high-speed mode before making a transition to watch mode or sub-active mode.
Figure 23.1 Mode Transition Diagram