Datasheet

Rev. 3.00, 03/04, page 621 of 830
Table 20.3 Register/Parameter and Target Mode
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Initiali-
zation
Program-
ming Erasure Read
FCCS    
FPCS    
FECS    
FKEY  
FMATS   *
1
*
1
*
2
Programming/
Erasing Interface
Register
FTDAR
   
DPFR    
FPFR  
FPEFEQ    
FMPAR    
FMPDR    
Programming/
Erasing Interface
Parameter
FEBS   

Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
20.3.1 Programming/Erasing Interface Register
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. These registers are initialized at a reset or in hardware standby mode.