Datasheet

Rev. 3.00, 03/04, page 603 of 830
Table 18.3 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1*
Item Symbol min typ max min typ max
A/D conversion start delay time t
D
10  17 6  9
Input sampling time t
SPL
 63   31 
A/D conversion time t
CONV
259  266 131  134
Notes: Values in the table indicate the number of states.
* in the table indicates that the system clock (φ) is 16 MHz or lower.
18.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit has been set to 1 by software. Figure 18.3 shows the
timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 18.3 External Trigger Input Timing