Datasheet

IFHSTL1A_010020030700 Rev. 3.00, 03/04, page 589 of 830
Section 17 D/A Converter
17.1 Features
• 8-bit resolution
• Two output channels
• Conversion time: Max. 10 µs (when load capacitance is 20 pF)
• Output voltage: 0 V to AVref
• D/A output retaining function in software standby mode
Module data bus Internal data bus
AVref
AVCC
DA1
DA0
AVSS
8-bit D/A
Control circuit
D
A
D
R
0
D
A
D
R
1
D
A
C
R
[Legend]
DACR: D/A control register
DADR0: D/A data register 0
DADR1: D/A data register 1
Bus interface
Figure 17.1 Block Diagram of D/A Converter