Datasheet

Rev. 3.00, 03/04, page 578 of 830
Table 16.8 Scope of LPC Interface Pin Shutdown
Abbreviation Port
Scope of
Shutdown I/O Notes
LAD3 to LAD0 PE3 to PE0 O I/O Hi-Z
LFRAME PE4 O Input Hi-Z
LRESET PE5 X Input LPC hardware reset function is active
LCLK PE6 O Input Hi-Z
SERIRQ PE7 O I/O Hi-Z
LSCI PD0 ∆ I/O Hi-Z, only when LSCIE = 1
LSMI PD1 ∆ I/O Hi-Z, only when LSMIE = 1
PME PD2 ∆ I/O Hi-Z, only when PMEE = 1
GA20 PD3 ∆ I/O Hi-Z, only when FGA20E = 1
CLKRUN PD4 O I/O Hi-Z
LPCPD PD5 X Input Needed to clear shutdown state
Notes: O: Pins shut down by the shutdown function
∆: Pins shut down only when the LPC function is selected by register setting
X: Pins not shut down
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by STBY or RES pin input, or WDT0 overflow)
 All register bits, including bits LPC3E to LPC1E, are initialized.
2. LPC hardware reset (reset by LRESET pin input)
 LRSTB, SDWNE, and SDWNB bits are cleared to 0.
3. LPC software reset (reset by LRSTB)
 SDWNE and SDWNB bits are cleared to 0.
4. LPC hardware shutdown
 SDWNB bit is cleared to 0.
5. LPC software shutdown
The scope of the initialization in each mode is shown in table 16.9.