Datasheet

Rev. 3.00, 03/04, page 569 of 830
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 16.2 and 16.3.
ADDRStart
LFRAME
LAD3 to LAD0
Number of clocks
LCLK
TAR Sync Data TAR Start
Cycle type,
direction,
and size
114 12221
Figure 16.2 Typical LFRAME Timing
ADDRStart
LFRAME
LAD3 to LAD0
LCLK
TAR Sync
Cycle type,
direction,
and size
Slave must stop driving
Too many Syncs
cause timeout
Master will
drive high
Figure 16.3 Abort Mechanism
16.4.3 SMIC Mode Transfer Flow
Figure 16.4 shows the write transfer flow and figure 16.5 shows the read transfer flow in SMIC
mode.