Datasheet

Rev. 3.00, 03/04, page 568 of 830
If the received address matches the host address in an LPC register, the LPC interface enters the
busy state; it returns to the idle state by output of a state #12 turnaround. Register (IDR, etc.) and
flag (IBF, etc.) changes are made at this timing, so in the event of a transfer cycle forced
termination (abort) before state #12, registers and flags are not changed.
Table 16.5 I/O Read and Write Cycles
I/O Read Cycle I/O Write Cycle
State
Count Contents
Drive
Source
Value
(3 to 0) Contents
Drive
Source
Value
(3 to 0)
1 Start Host B'0000 Start Host B'0000
2 Cycle type/direction Host B'0000 Cycle type/direction Host B'0010
3 Address 1 Host Bits 15 to
12
Address 1 Host Bits 15 to
12
4 Address 2 Host Bits 11 to 8 Address 2 Host Bits 11 to 8
5 Address 3 Host Bits 7 to 4 Address 3 Host Bits 7 to 4
6 Address 4 Host Bits 3 to 0 Address 4 Host Bits 3 to 0
7 Turnaround
(recovery)
Host B'1111 Data 1 Host Bits 3 to 0
8 Turnaround None B'ZZZZ Data 2 Host Bits 7 to 4
9 Synchronization Slave B'0000 Turnaround
(recovery)
Host B'1111
10 Data 1 Slave Bits 3 to 0 Turnaround None B'ZZZZ
11 Data 2 Slave Bits 7 to 4 Synchronization Slave B'0000
12 Turnaround
(recovery)
Slave B'1111 Turnaround
(recovery)
Slave B'1111
13 Turnaround None B'ZZZZ Turnaround None B'ZZZZ